1. Field of the Invention
This invention relates generally to semiconductor integrated circuit memory devices and particularly relates to such synchronous dynamic random access memory devices (SDRAMs) sending and receiving bursts of data synchronous with a clock signal.
2. Description of the Related Art
DRAMs are used in desktop and other computers and other electronic machines needing memory devices. Common reasons for using DRAMs include their providing the greatest density of memory cells on a semiconducting chip, relative low cost per bit of stored data and relatively high speed for their cost. With advances in technology, each generation of DRAM memory devices has increased the number of memory cells on a chip by a factor of four. With more recent microprocessors operating at 100 Megahertz and above, faster DRAMs are needed to supply data and instructions to the microprocessor.
With this need for larger storage capacity and greater speed, DRAMs have evolved that synchronize the transfer of data, addresses and control signals with a clock signal. These requirements for larger storage capacity and greater speed also raise new difficulties in designing the circuits constituting and the processes for manufacturing a DRAM memory device.
In prior DRAM memory devices, the bond pads on the semiconductor substrate occurred at one location with storage of the data signals occurring at other spaced locations on the substrate. Relatively long data lines occurred on the substrates to convey the data between the bond pads and storage locations. This led to large parasitic capacitances in the data lines that required larger drive circuits. The parasitic capacitances and resulting high power required to drive the devices prevented an economical device from operating at 100 megahertz or faster.
Data also must be written into and read from the synchronous DRAM devices in one of two different modes: serial and interleaved. In serial mode, the data occurs in the same sequence as its serial addresses. In interleaved mode, the data occurs in a certain, well-defined sequence other than sequential. Implementing a synchronous DRAM device can be accomplished in either a pipelined or pre-fetch architecture; in either case, provisions must be made to achieve operation in both the serial and interleaved data modes.